module top(
    input   logic        clk, reset,
    output  logic [31:0] writedata, dataaddr,
    output  logic        memwrite
);

 wire [31:0] pc, instr, readdata;

 mips mips(clk, reset, pc, instr, memwrite, dataaddr, writedata, readdata);
 imem imem(pc[7:2], instr);
 dmem dmem(clk, memwrite, dataaddr, writedata, readdata);

endmodule